Model Order Reduction Techniques for Circuit Simulation

Theoretical and practical aspects of model order reduction techniques for use in the context of circuit simulation are investigated, with particular attention to problems involving clocked analog circuitry and to interconnect and packaging applications. First, an algorithm for the efficient simulation of clocked analog circuits is described and simulation results are presented. Traditional simulation programs, which must accurately solve the associated differential equations with a time discretization method become extraordinarily computationally expensive when applied to simulating the transient behavior of clocked analog circuits. These circuits are clocked at a frequency whose period is typically orders of magnitude smaller than the time interval of interest to the designer. The nature of the calculations requires that in order to construct the solution over the time interval of interest, an accurate solution must be computed for every cycle of the high frequency clock in the interv..