On Evaluating Competing Bridge Fault Models for CMOS ICs

We compare the accuracy, speed and applicability to test generation of existing bridge fault modeling solutions. We identify some previously undiscussed anomalous circuit behaviors, and describe the extent to which they affect bridge fault simulation and testing. Finally, we present a system for evaluating bridge fault models in a test generation environment, and we present an experiment that provides an assessment of how defect coverage can be affected by a generating and checking model. 1 Introduction In the search for IC quality, realistic defect testing is becoming increasingly important. In order to obtain the relatively modest quality level of 200 defective parts per million (DPM) in a circuit with a 90% yield requires that the test set detect 99.8% of the manufacturing defects [WB81, MB88]. The majority of spot defects in current MOS technologies cause changes in the circuit description that result in shorts [FM91]. Tests that cover 100% of the testable single stuck-at faults m..