Techniques for Low-Overhead and No-Overhead Communication Using Commodity Superscalar Processors

Previous researchers in user-level message-passing parallel computing have attempted to reduce communication overhead via several techniques: integrating part or all of the network interface (NI) on the CPU[8, 2], allowing NI device register accesses to be cached[11, 6], or using polling to avoid the overhead of interrupts[15, 18]. Unfortunately, these techniques incur significant overhead if applied to a superscalar processor system. We have developed architectural features that have the potential to alleviate these overheads. In this paper we present the results of simulations which demonstrate successful overlap of communication overhead and network latency with useful work. This benefit was achieved without sacrificing programmibility --- our message-passing libraries use PVM semantics. 1 Introduction Developments in processor design have created CPUs that are able to find and exploit low-level parallelism in sequential code through techniques such as pipelining, superscalar issue..