Earlier work has demonstrated that partitioning one large behavioral process into smaller ones before synthesis can yield numerous advantages, such as reduced synthesis runtime, easier package constraint satisfaction, reduced power consumption, improved performance, and hardware/software tradeo#s. In this paper, we describe a novel three-step functional partitioning methodology for automatically dividing a large behavioral process into mutually-exclusive subprocesses, and we define the problems and our solutions for each step. The three steps are granularity selection, pre-clustering, and N-way assignment. We refer to experiments throughout that demonstrate the e#ectiveness of the solutions. 1 Introduction Functional partitioning divides ...
This paper presents a new performance-driven partitioning method for multi-FPGA designs. The propose...
In this paper, we present a functional partitioning method for low power real-time distributed embed...
[[abstract]]This paper presents a new performance-driven partitioning method for multi-FPGA designs....
Many approaches have been developed to partition a system's behavioral description before a structur...
Functional partitioning assigns the functions of a system 's program-like specification among s...
International audienceThis paper presents a methodology and a tool for system-level partitioning in ...
This paper presents a new method for behavioural partitioning at the system level. The method is bas...
This paper presents a methodology and a tool box for system-level partitioning in the behavioral dom...
Abstract: In this paper, we study the problem of behavioral-level partitioning for low power design....
The problem of hardware-software partitioning for systems that are being designed as multifunction s...
[[abstract]]The authors present methods for scheduling and partitioning behavioral descriptions in o...
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and highlevel...
In this paper a new approach for partitioning designs on the behavioral level is presented. Our main...
As witnessed by their recent rapid market growth, reconfigurable multi-functional data paths are an ...
In this paper, an algorithm is presented for decomposing a system into IP (Intellectual Property) fu...
This paper presents a new performance-driven partitioning method for multi-FPGA designs. The propose...
In this paper, we present a functional partitioning method for low power real-time distributed embed...
[[abstract]]This paper presents a new performance-driven partitioning method for multi-FPGA designs....
Many approaches have been developed to partition a system's behavioral description before a structur...
Functional partitioning assigns the functions of a system 's program-like specification among s...
International audienceThis paper presents a methodology and a tool for system-level partitioning in ...
This paper presents a new method for behavioural partitioning at the system level. The method is bas...
This paper presents a methodology and a tool box for system-level partitioning in the behavioral dom...
Abstract: In this paper, we study the problem of behavioral-level partitioning for low power design....
The problem of hardware-software partitioning for systems that are being designed as multifunction s...
[[abstract]]The authors present methods for scheduling and partitioning behavioral descriptions in o...
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and highlevel...
In this paper a new approach for partitioning designs on the behavioral level is presented. Our main...
As witnessed by their recent rapid market growth, reconfigurable multi-functional data paths are an ...
In this paper, an algorithm is presented for decomposing a system into IP (Intellectual Property) fu...
This paper presents a new performance-driven partitioning method for multi-FPGA designs. The propose...
In this paper, we present a functional partitioning method for low power real-time distributed embed...
[[abstract]]This paper presents a new performance-driven partitioning method for multi-FPGA designs....