In this paper, we mainly present a fast, stable and efficient module placement algorithm which is based on PROUD algorithm and its improved modified version. The PROUD algorithm uses a hierarchical decomposition technique and the solution of sparse linear systems based on a resistive network analogy. It has been shown that the PROUD algorithm can achieve a comparable design of the placement problems for very large circuits with the best placement algorithm based on simulated annealing, but with several order of magnitude faster. The modified PROUD, namely MPROUD algorithm by perturbing the coefficient matrices performs much faster that the original PROUD algorithm. Due to the instability and unguaranteed convergence of MPROUD algorithm, we ...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
[[abstract]]There are many algorithms for automatic placement in IC layout design. However, as chips...
In this paper, we propose a heuristic procedure for finding near-optimal placement of VLSI circuit m...
In this paper, we propose a heuristic procedure for finding near-optimal placement of VLSI circuit m...
[[abstract]]A fast and effective placement algorithm is presented which takes advantage of inherent ...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
This paper studies the optimality, scalability and stability of state-of-the-art partitioning and pl...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
by Li Wai Ting.Thesis (M.Ph.)--Chinese University of Hong Kong, 1987.Includes bibliographical refere...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
Conventional simulated annealing algorithm, which works on the flattened circuit, has a very large s...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
[[abstract]]There are many algorithms for automatic placement in IC layout design. However, as chips...
In this paper, we propose a heuristic procedure for finding near-optimal placement of VLSI circuit m...
In this paper, we propose a heuristic procedure for finding near-optimal placement of VLSI circuit m...
[[abstract]]A fast and effective placement algorithm is presented which takes advantage of inherent ...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
This paper studies the optimality, scalability and stability of state-of-the-art partitioning and pl...
As modern VLSI designs have become larger and more complicated, the computational requirements for d...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
The computational requirements for high quality synthesis, analysis, and verification of VLSI design...
by Li Wai Ting.Thesis (M.Ph.)--Chinese University of Hong Kong, 1987.Includes bibliographical refere...
As technology advances, the effect of intra-module delays become less significant, while the effect ...
Conventional simulated annealing algorithm, which works on the flattened circuit, has a very large s...
: The paper deals with a problem encountered in the physical implementation of circuits on the PCB a...
[[abstract]]We survey recent development in placement technology for VLSI layout. In the very deep s...
As technology advances, the effect of intra-module delays become less significant, while the effect ...