Clock Level Simulations Of An Atm Switch

We simulate an ATM VPI-switch with pipelined (or shared-slot data buffer) and output buffering. Our experiments for 2 \Theta 2 and 4 \Theta 4 switches under constant and time-variant traffic indicate that both switches and memory organizations have near-optimal throughput. Assuming switches are of similar technology, multistage network experiments under constant traffic indicate that 4 \Theta 4 and 16 \Theta 16 networks configured with smaller 2\Theta2 switches achieve higher performance. However, networks configured with larger switches are more cost-efficient. 1 INTRODUCTION ATM is an embrace of developments in circuit and packet switching, allowing for multiple logical connections to be multiplexed over a single physical link (Vetter and Du 1995). These connections are identified by unique virtual path (VPI=12 bits) and virtual circuit (VCI=16 bits) identifiers. The packet size is fixed to 53 bytes, with 48 bytes data and 5 bytes header information. Previous link-to-link header an..