Add to ORKGWe present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs based on the pre-determined testing conditions of cells in the standard cell library. In a one-time effort, fabrication level defects in each cell in the standard cell library are extensively analyzed via circuit simulations. Optimal test sequence of each cell is then determined and pre-stored for later use. For a given circuit under test (CUT), the automatic test sequence generation (ATSG) program generates the test sequence of the circuit under test by trying to satisfy all test sequences of all cells in the given netlist. The results on ISCAS85 benchmark circuits show that the proposed approach reduces test generation time and test size si...
Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly re...
The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufac...
Test pattern generation has progressed to a stage at which automatic test generation gives satisfact...
We present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs ...
This paper describes use of a previously proposed test generation program named Jethro to detect the...
This paper describes the use of a previously proposed test generation program named Jethro [1] on te...
Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (...
This research is focused on the development of a hierarchical test generation methodology of intra-c...
Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve te...
This dissertation describes a new test generation method in which the test vectors or test sequences...
The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufac...
Two approaches have been used to balance the cost of generating effective tests for IC's and th...
Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high ...
It is assumed that tests generated using the single stuck-at fault model will implicitly detect the ...
An efficient automatic test pattern generator for I$\sb{DDQ}$ current testing of CMOS digital circui...
Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly re...
The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufac...
Test pattern generation has progressed to a stage at which automatic test generation gives satisfact...
We present in this paper a new concept of test sequence generation for realistic faults in CMOS ICs ...
This paper describes use of a previously proposed test generation program named Jethro to detect the...
This paper describes the use of a previously proposed test generation program named Jethro [1] on te...
Due to their large number of high-precision, defect-prone manufacturing steps, integrated circuits (...
This research is focused on the development of a hierarchical test generation methodology of intra-c...
Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve te...
This dissertation describes a new test generation method in which the test vectors or test sequences...
The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufac...
Two approaches have been used to balance the cost of generating effective tests for IC's and th...
Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high ...
It is assumed that tests generated using the single stuck-at fault model will implicitly detect the ...
An efficient automatic test pattern generator for I$\sb{DDQ}$ current testing of CMOS digital circui...
Cell-aware test (CAT) explicitly targets defects inside library cells and therefore significantly re...
The fabrication process of modern integrated circuits (ICs) is not perfect and the resulting manufac...
Test pattern generation has progressed to a stage at which automatic test generation gives satisfact...