A Unified Lower Bound Estimation Technique for High-Level Synthesis The importance of effective lower bound estimation (LBE) techniques is well-established in HighLevel Synthesis (HLS), since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. With the push towards sub-micron technologies, simple models that use functional unit resources alone are not accurate enough to allow effective design space exploration since the effects of storage and interconnect can indeed dominate the cost...
In this thesis, circuit parameters that are related to low power/energy high level synthesis for VLS...
A value approximation-based global search algorithm is suggested to solve resource-constrained alloc...
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is ...
International audienceHigh-level synthesis (HLS) currently seems to be an interesting process to red...
This thesis is an effort in the area of electronic design automation applied to system-level modelin...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Abstract—Achieving design closure is one of the biggest chal-lenges for modern very large-scale inte...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
High Level Synthesis (HLS) is a process which, starting from a high-level description of an applicat...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
Nowadays hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate A...
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-leve...
In this paper a unified approach of lower bound functional area and cycle budget estimations is pres...
This work is a contribution to high level synthesis for low power systems. While device feature size...
Abstract--- High-level estimation techniques are of paramount importance for design decisions like h...
In this thesis, circuit parameters that are related to low power/energy high level synthesis for VLS...
A value approximation-based global search algorithm is suggested to solve resource-constrained alloc...
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is ...
International audienceHigh-level synthesis (HLS) currently seems to be an interesting process to red...
This thesis is an effort in the area of electronic design automation applied to system-level modelin...
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled da...
Abstract—Achieving design closure is one of the biggest chal-lenges for modern very large-scale inte...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
High Level Synthesis (HLS) is a process which, starting from a high-level description of an applicat...
Decisions taken at the earliest steps of the design process may have a significant impact on the cha...
Nowadays hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate A...
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-leve...
In this paper a unified approach of lower bound functional area and cycle budget estimations is pres...
This work is a contribution to high level synthesis for low power systems. While device feature size...
Abstract--- High-level estimation techniques are of paramount importance for design decisions like h...
In this thesis, circuit parameters that are related to low power/energy high level synthesis for VLS...
A value approximation-based global search algorithm is suggested to solve resource-constrained alloc...
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is ...