Hardware Synthesis for Neural Networks from a Behavioral Description with VHDL

In this paper we present a system for automatic synthesis of special purpose hardware for neural networks. Only an algorithmic description of the behaviour of the hardware and a simulation environment have to be written by the designer using VHDL. This description can be automatically mapped onto hardware using the synthesis tool CALLAS and the design system MENTOR. Using the concept of a simulation block connected to the actual design level of the hardware implementation the consistency of the different design levels can be proved. By using reprogrammable gate arrays (FPGAs) with this system we are able to do rapid prototyping of neural network hardware in a few days