Packet Scheduling for WDM Fiber Delay Line Buffers in Photonic Packet Switches

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced by its architecture and the packet scheduling algorithm