Design of CMOS Dynamic Circuits with . . .

this paper we present a new noise-tolerant dynamic circuit technique suitable for pipelined dynamic digital circuits. The effectiveness of this technique is demonstrated by means of HSPICE simulations for two kind of gates, CMOS AND and OR gates, both TSPC and Domino. In order to have a clear idea about this proposal's noise immunity improvement we compare its performance with previous works. Simulation results show that the proposed technique has an improvement in the noise tolerance and the 9999 quotient over the conventional dynamic logic and the previous noise-tolerant dynamic circuit techniques with a slight delay and power increas