This paper describes an approach to hardware /software design space exploration for reconfigurable processors. The existing compiler tool-chain, because of the user-definable instructions, needs to be extended in order to offer developers an easy way to explore design space. Such extension often is not easy to use for developer that have only a software background, thus ignoring reconfigurable architecture details or hardware logic synthesis on FPGA. Our approach differs from others because it is based on a simple extension on the standard programming model well known to software developers
Abstract: The traditional design space exploration methodology suits the single processor system-on-...
Thesis (Ph.D.)--University of Kansas, Electrical Engineering & Computer Science, 2007.Reconfigurable...
This demonstration presents a tool ow, based on a speci-cation formalism and assisted by instructio...
International audienceMany reconfigurable hardware architectures have been proposed so far, ranging ...
The capability to tailor the processor instruction set architecture (ISA) around the computational r...
This paper describes an automated approach to hardware design space exploration, through a collabora...
Abstract—This paper presents the design alternatives for reconfigurable instruction set processors (...
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the...
Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumpt...
Reducing both cost and time-to-market while increasing performance, resource utilization, and reliab...
Abstract—The process of embedded system design on reconfig-urable architectures needs smart solution...
The current paper reports on the first results of building a retargetable compiler for reconfigurabl...
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing ...
This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamica...
Reconfigurable Computing is emerging as an important new organizational structure for implementing c...
Abstract: The traditional design space exploration methodology suits the single processor system-on-...
Thesis (Ph.D.)--University of Kansas, Electrical Engineering & Computer Science, 2007.Reconfigurable...
This demonstration presents a tool ow, based on a speci-cation formalism and assisted by instructio...
International audienceMany reconfigurable hardware architectures have been proposed so far, ranging ...
The capability to tailor the processor instruction set architecture (ISA) around the computational r...
This paper describes an automated approach to hardware design space exploration, through a collabora...
Abstract—This paper presents the design alternatives for reconfigurable instruction set processors (...
Reconfigurable instruction set processors have the capability to adapt their instruction sets to the...
Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumpt...
Reducing both cost and time-to-market while increasing performance, resource utilization, and reliab...
Abstract—The process of embedded system design on reconfig-urable architectures needs smart solution...
The current paper reports on the first results of building a retargetable compiler for reconfigurabl...
Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing ...
This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamica...
Reconfigurable Computing is emerging as an important new organizational structure for implementing c...
Abstract: The traditional design space exploration methodology suits the single processor system-on-...
Thesis (Ph.D.)--University of Kansas, Electrical Engineering & Computer Science, 2007.Reconfigurable...
This demonstration presents a tool ow, based on a speci-cation formalism and assisted by instructio...