A 1.6Gb/s, 3mW Integrating CMOS Optical Receiver with Hybrid GaAs Photo-Detectors

the bit rate is limited by the sample bandwidth and input sensitivity of the sense amp, and not the gain-bandwidth of an amplifier. Higher data rates can be achieved using more samplers, clocked sense amps, and multi-phase clocks. The key issue in the design of this receiver is dealing with small input signals needed for low optical power detection, thus the clocks and the sense amps need to be designed to minimize the noise and offset of the receiver. The circuit also needs to create a reference current to convert the singleended, positive photo current to a bipolar current. Figure 1:Receiver block diagram The signal path starts from the pass-gate samplers, with two non-overlapping phases, f that sample at both rising and falling edges of reference clock. The non-overlapping clocks allows one to activate the sense amp when both samplers are in the hold mode, making any charge injection common mode. The two hold capacitors consist mostly of the input capacitance of the sense a