Zero Skew Clock-Tree Optimization with Buffer Insertion/Sizing and Wire Sizing

Cloc distribution iscvV(Nj for timing and designcsi vergenc in high-performanc very largescVN integration designs. Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long beencenvVjV ed intracv2(V) In this paper, we presentClm kTune, a simultaneous buffer insertion/sizing and wire-sizing algorithmwhic guarantees zero skew and minimizes delay and power in polynomial time. Extensive experimental results show that our algorithm execrit very efficvN----P . For example,ClI kTuneacv6 ves 45 delay improvement for buffering and sizing an industrialcndu tree with 3101 sink nodes on a 1.2-GHz Pentium IV PC in 16 min,cn,vV ed with the initial routing. Our algorithmco also be used toacVU ve usefulcefu skew to facUNV:v2 timingcm vergenc and toinc ementally adjust thecev6 tree for designcs vergenc and explore delay--power tradeoffs during designcs csi Cl kTune is available on the web (http://vlsi.ecvvVN)(Vv2--6 ools.htm). Index Terms---Buffer insertion, buffer sizing,czin tree, optimization, wire sizing, zero skew