This report is issued to provide documentation for the benchmark examples used in conjunction with the 1991 MCNC International Workshop on Logic Synthesis and the extention of the 1989 Logic Synthesis and Optimization Benchmarks User Guide. Its distribution is limited to peer communication and to participants of the workshop. This report contains material previously published and distributed by the University of California (Copyright 1979, 1980, 1983, 1986 Regents of the University of California) and Stanford University. For information about the ideas expressed herein, contact the author(s) directly. For information about the MCNC Technical Report Series, or Industrial Affiliates Program, contact Corporate Communications, MCNC, P.O. Box 12...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
<p>The software requires access to a library of characterized parts (such as a subset of the parts a...
Abstract – Benchmark designs are the basis for the performance evaluation of today’s EDA tools for a...
Includes bibliographical references (leaf [73])A logic synthesis tool called LST is developed. This ...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during ...
This dataset comprises all the necessary data to reproduce the obtained results presented in the man...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
The EPFL Combinational Benchmark Suite was introduced in 2015 with the aim of defining a new compara...
This report describes the current status of benchmarks for the 1992 High-Level Synthesis Workshop an...
in Logic Based Program Synthesis and Transformation, Revised Selected Papers, ed. Michael Leuschel, ...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Benchmark circuits used in the work entitled "Don't-care-based node minimization for threshold logic...
Due to the character of the original source materials and the nature of batch digitization, quality ...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
<p>The software requires access to a library of characterized parts (such as a subset of the parts a...
Abstract – Benchmark designs are the basis for the performance evaluation of today’s EDA tools for a...
Includes bibliographical references (leaf [73])A logic synthesis tool called LST is developed. This ...
In this thesis, new algorithms for logic synthesis areexplored. Our work is motivated by two observa...
Logic synthesis is a challenging and widely-researched combinatorial optimization problem during ...
This dataset comprises all the necessary data to reproduce the obtained results presented in the man...
As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex ...
The EPFL Combinational Benchmark Suite was introduced in 2015 with the aim of defining a new compara...
This report describes the current status of benchmarks for the 1992 High-Level Synthesis Workshop an...
in Logic Based Program Synthesis and Transformation, Revised Selected Papers, ed. Michael Leuschel, ...
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can...
Benchmark circuits used in the work entitled "Don't-care-based node minimization for threshold logic...
Due to the character of the original source materials and the nature of batch digitization, quality ...
This thesis introduces new concepts to perform area-power-delay trade-offs in a logic synthesis syst...
First, an analytical method for the minimization of multiple-valued input Boolean functions is inves...
<p>The software requires access to a library of characterized parts (such as a subset of the parts a...