Boundary Element Methods for Capacitance and Substrate Resistance Calculations in a VLSI Layout Verification Package

In this paper we describe the application of the Boundary Element Method to the layout verification of VLSI Designs. We describe the methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Green's functions. Emphasis is on computational efficiency and practical accuracy. The methods are implemented in the layout extractor Space (van der Meijs [1]). INTRODUCTION Designers of modern VLSI circuits rely heavily on layout-to-circuit extractors, which translate a chip layout into an equivalent network suitable for electrical verification of their layouts. Because of the growing influence of parasitic elements, such extractors must be able to model (extract) more and more parasitic phenomena. Parasitic capacitances and coupling between different components via the substrate of the chip are severe problems, see e.g. Bakoglu [2] and Kup [3]. We describe Boundary Element Methods for the calculation of interconnection capacitances an..