Add to ORKGthis paper, we consider different ways to design and optimize a delay-insensitive modulo-N counter as a case study to several discover principles of design optimization. We show circuit implementations that are comparable in area with their best synchronous counterparts, while at the same time providing higher speed and lower power requirements than competing designs. While this hardly constitutes a general approach to opti2 mizing area, power, and speed for DI circuits, it does serve as an indication that surprisingly good results can be achieved simultaneously in all three dimensions if proper design optimizations are employed. 2 A formal model and a language of specificatio
The most valuable asset we are given is time. This is perhaps the main motivation behind the desire ...
Abstract. There are two ways to design a digital circuit. Covering methods are widely used which inc...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
Various delay-insensitive circuits for modulo-N counters are formally derived and analyzed. Modulo-N...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Deep submicron technology calls for new design techniques, in which wire and gate delays are account...
The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on ...
textLogic optimization and clock network optimization for power, performance and area trade-off have...
Low power oriented circuit optimization consists in selecting the best alternative between gate sizi...
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investi...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
Global optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep ...
A multiplier circuit used in digital electronics is basically to multiply two or more numbers. Multi...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
The most valuable asset we are given is time. This is perhaps the main motivation behind the desire ...
Abstract. There are two ways to design a digital circuit. Covering methods are widely used which inc...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...
Various delay-insensitive circuits for modulo-N counters are formally derived and analyzed. Modulo-N...
Due to the character of the original source materials and the nature of batch digitization, quality ...
Deep submicron technology calls for new design techniques, in which wire and gate delays are account...
The relentless push for high performance in custom dig-ital circuits has led to renewed emphasis on ...
textLogic optimization and clock network optimization for power, performance and area trade-off have...
Low power oriented circuit optimization consists in selecting the best alternative between gate sizi...
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investi...
This paper presents a unified model for delay estimation in various CMOS logic styles. It also deriv...
Global optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep ...
A multiplier circuit used in digital electronics is basically to multiply two or more numbers. Multi...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
[[abstract]]As feature sizes shrink to deep sub-micron, the performance of VLSI chips becomes domina...
The most valuable asset we are given is time. This is perhaps the main motivation behind the desire ...
Abstract. There are two ways to design a digital circuit. Covering methods are widely used which inc...
In this thesis, we address the problem of optimizing sequential logic circuits for low power. We pre...