Using Transformation to Reduce Power Consumption of IS-95 CDMA Receiver

In this paper, we address the issues of designing low power VLSI implementation of the Code Division Multiple Access (CDMA) receiver targeting IS-95. We demonstrate the use of architectural transformation to reduce the power consumption of the two most computational intensive and power-hungry digital blocks of a CDMA receiver, namely the RAKE receiver and the Viterbi decoder. In particular, the architecture of the RAKE receiver is transformed to reduce the operational frequency of the arithmetic components and we propose a new AddCompare -Select (ACS) architecture for the Viterbi decoder which can reduce the complexity of the computation. Also after the transformation, clock-gating technique using pre-computational architecture is used to further reduce the power consumption of the ACS unit. Experimental results show significant reduction in power consumption. 1. Introduction Transformation and clock gating technique are two very effective methods in reducing power consumption. Differ..