A Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits

Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A sufficient condition for a multilevel unate circuit to be "hazard free delay fault testable" is presented. In contrast to existing results that consider either "single path propagating hazard free robust tests" or "general robust tests" we consider "multiple path propagating hazard free robust tests" in our analysis. INDEX TERMS: Delay Fault Testable Circuits; Logic Optimization; Robust Tests; Testability Enhancing Transformations; Testability Preserving Transformations. 1 Introduction Delay testing attempts to verify the timing specifications of circuits. Of the two delay models, path delay[8, 12, 13, 17, 21] and gate delay[8] we use path delay fault model. In this model, along every physical path, from an input to an output of the combinational circuit, two distinct transitions - P f , input fa..