Hierarchical Decomposition of High Level Timed Petri Nets

In IPTES, real-time system specifications expressed in SA/SD-RT are internally represented by means of High Level Timed Petri Nets (HLTPNs). Petri nets present several widely recognized advantages, however their usefulness is limited by the absence of hierarchical decomposition mechanisms. The absence of hierarchical decomposition mechanisms has at least three main consequences on the usability of Petri nets for the specifications of real size systems: fast growth of the specifications that become quickly unreadable: impossibility of mapping the hierarchical aspects of specifications expressed in a hierarchical language (e.g. SA/SD-RT) directly onto Petri nets; no support for reducing the analysis effort by means of divide and conquer strategies based on a suitable hierarchy. This report presents a formal hierarchical decomposition mechanism for HLTPNs, that it can enhance existing analysis techniques, support mapping from hierarchical specification languages, and improve the readabili..