INTRODUCTION This manual is meant as a guide to users who want to simulate their network with the sls simulator. The acronym sls stands for Switch-Level Simulator, and the simulator can be used for simulating the logical and timing behavior of digital MOS circuits. In the simulator transistors are modeled by grounded capacitors and a switched resistor. Each node in the network has a logic state O, I or X (for unknown), and each transistor has a state on, off or undefined. Many characteristics of MOS circuits can be modeled accurately, including: ratioed, complementary and precharged logic; dynamic and static storage; pass transistors; busses; and charge sharing. Because the simulator performs local-event-driven simulation, large networks ...
Gate level simulators are those which simulate digital logic circuits composed only of basic gates s...
The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
The switch-level model describes the logical behavior of digital systems implemented in metal oxide ...
The switch-level model describes the logical behavior of digital circuits implemented in metal ox...
INTRODUCTION In this manual it is explained how function blocks can be used in the Switch-Level Sim...
Switch-level simulation has become an indispensable tool in the verification of large MOS circuits. ...
Lsim2 is gate/switch-level digital logic simulator. It enables users to model digital circuits both ...
Lsim is a gate/switch level digital logic similar. It enables users to model digital circuits both a...
245 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.This dissertation deals with ...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
Design of high performance hardware and software based gate-switch level logic simulators requires k...
This paper presents a method to automatically recog-nize and model single and multi-output logic gat...
A timing simulator, called TIMSIM, has been developed which performs gate level simulation of simple...
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circui...
Gate level simulators are those which simulate digital logic circuits composed only of basic gates s...
The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...
The switch-level model describes the logical behavior of digital systems implemented in metal oxide ...
The switch-level model describes the logical behavior of digital circuits implemented in metal ox...
INTRODUCTION In this manual it is explained how function blocks can be used in the Switch-Level Sim...
Switch-level simulation has become an indispensable tool in the verification of large MOS circuits. ...
Lsim2 is gate/switch-level digital logic simulator. It enables users to model digital circuits both ...
Lsim is a gate/switch level digital logic similar. It enables users to model digital circuits both a...
245 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1985.This dissertation deals with ...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
Design of high performance hardware and software based gate-switch level logic simulators requires k...
This paper presents a method to automatically recog-nize and model single and multi-output logic gat...
A timing simulator, called TIMSIM, has been developed which performs gate level simulation of simple...
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circui...
Gate level simulators are those which simulate digital logic circuits composed only of basic gates s...
The purpose of this research is to develop a cost effective timing simulator for digital metal-oxide...
Circuit Simulation is a critical bottleneck in VLSI design. This paper describes a parallel switch-l...