Performance-Oriented Placement and Routing for Field-Programmable Gate Arrays

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graphbased strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks. 1 Introduction Field-programmable gate arrays, or FPGAs, afford designers a versatile and inexpensive way to implement and test VLSI designs [5, 10]. FPGAs are available in a number of styles and configurations [29]. One of the most common FPGA architectures consists of symmetrical arrays of user-configurable logic blocks interconnected by a set of programmable routing resources [32] (Figure 1). FPGA reprogrammability is achieved at the expense of performance, i.e., long signal delays through the reconfigurab..