Superspeculative Microarchitecture for Beyond AD 2000

C, these machines typically achieve only about 0.5 to 1.5 sustained IPC for real-world programs. Worse yet, most studies indicate that machine efficiency drops even lower as we extrapolate to wider machines. One recent study indicated that although a hypothetical 2-instruction-wide machine achieves IPC in the range of 0.65 to 1.40, a similar, hypothetical, 6-instruction-wide machine will achieve only 1.2 to 2.3 IPC. 1 Such data imply that the current superscalar paradigm is running into rapidly diminishing returns on performance. POTENTIAL NEW PARADIGMS Future billion-transistor chips will inevitably implement machines that are much wider (issue more than four instructions at once) and deeper (have longer pipelines). The question is, how do we harvest additional parallelism proportional to increased machine resources? Several approaches have vocal advocates, each with valid reasons; they are . reconfigurable parallel computing engines; . specializ