Towards a High-Level Power Estimation Capability

We will present a power estimation technique for digital integrated circuits that operates at the register transfer level (RTL). Such a high-level power estimation capability is required in order to provide early warning of any power problems, before the circuit-level design has been specified. Our estimator is based on the use of entropy as a measure of the average activity to be expected in the final implementation of a circuit, given only its Boolean functional description. This technique has been implemented, and empirical results will be presented that demonstrate the feasibility and utility of this approach. I. INTRODUCTION The high device count and operating frequency of modern integrated circuits has led to unacceptably high levels of chip power consumption. For example, the PowerPC microprocessor from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's Alpha chip consumes 30 Watts. Due to limited battery life, high power consumption is a majo..