High-Level Power Estimation And The Area Complexity Of Boolean Functions

Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (RTL). This paper addresses the problem of computing the area complexity of single-output Boolean functions given only their functional description, where area complexity is measured in terms of the number of gates required for an optimal implementation of the function. We propose an area model to estimate the area based on a new complexity measure called the average cube complexity. This model has been implemented, and empirical results demonstrating its feasibility and utility are presented. 1. Introduction Rapid increase in the design complexity and the need to reduce design time have resulted in a need for CAD tools that can help make important design decisions early in the design process. To do so, these tools must operate with a design description at a high level of abstraction. One design criterion th..