Area And Performance Analysis Of Processor Configurations With Scaling Of Technology

As integrated circuit density increases, computer architects face the interesting problem of how best to utilize the available die size given cost and performance constraints. Traditionally, area partitioning and floor-planning have been done in an ad hoc fashion based on intuition and experience of the designers. This paper proposes a systematic methodology for correlating area and performance as the designer increases the transistor count of a given sub-unit. Specifically, we investigate the performance of three possible processor configurations, and present performance results as the mimimun feature size is reduced. Key Words and Phrases: cache, technology scaling, bus traffic, Area modeling, superscalar, multiprocessor Copyright c fl 1994 by Steve Fu and Michael Flynn Contents 1 Introduction 1 2 Processor Specifications 1 3 Methodology 6 4 Area Modeling 6 5 Cache Configuration Exploration 7 6 Cache Design 10 6.1 Unified versus Split : : : : : : : : : : : : : : : : : : : : : :..