Reconfigurable Signal Processor For Channel Coding & Decoding In Low SNR Wireless Communications

An area and computational-time efficient turbo decoder implementation on a reconfigurable processor is presented. The turbo decoder takes advantage of the latest sliding window algorithms to produce a design with minimal storage requirements as well as offering the ability to configure key system parameters via software. The parameter programmability allows the decoder to be used in a research environment to study less understood aspects of turbo codes. 1. INTRODUCTION The flexibility and quick response of FPGA technology to the changing market scene has led it to be utilized to perform a variety of different tasks. In the process, a natural progression in terms of usage has quietly been transpiring. At first, systems were used primarily for their rapid prototyping capability in industry and system emulation in academia, and this remains largely the case today. However, as more people become aware of the applications of configware, this is beginning to change. Furthermore, as partial..