. R2 is an attempt to create an interconnection component that provides reliable packet delivery services at low latency under bursty traffic situations and in the presence of certain faults in either the network or processing elements. The R2 design is based on a damped adaptive routing scheme that avoids livelock, exhibits improved latency under bursty congestion, while performing similar to deterministic strategies in the lightly loaded case. This paper describes the R2 architecture and presents the results of a simulation study which motivates the damped adaptive routing strategy employed by the R2 switch. 3 1 Introduction The work presented here is a natural extension of previous work on a high performance router called the ...
. As interconnection networks grow larger and larger, the need for reliable message delivery in the...
The design of a new adaptive virtual cut-through router for torus networks is presented in this pape...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...
The Reliable Router (RR) is a network switching element targeted to two-dimensional mesh interconnec...
The IBM RS 6000 SP is one of the most successful commercially available multicomputers. SP owes its ...
Cataloged from PDF version of article.The IBM RS 6000 SP is one of the most successful commercially ...
Throughput and latency are critical parameters in multiprocessor interconnection networks. These par...
A message transport mechanism which provides highbandwidth low-latency interprocessor communication ...
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication in...
Abstract: In this paper, we present several enhanced network techniques which are appropriate for VL...
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is propose...
The IBM RS/6000 SP is one of the most successful commercially available multicomputers. SP owes its ...
Recent increases in the pin bandwidth of integrated-circuits has motivated an increase in the degree...
Modern network applications demand low-latency traffic engineering in the presence of network failur...
Abstract — The increasing wire delay constraints in deep sub-micron VLSI designs have led to the eme...
. As interconnection networks grow larger and larger, the need for reliable message delivery in the...
The design of a new adaptive virtual cut-through router for torus networks is presented in this pape...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...
The Reliable Router (RR) is a network switching element targeted to two-dimensional mesh interconnec...
The IBM RS 6000 SP is one of the most successful commercially available multicomputers. SP owes its ...
Cataloged from PDF version of article.The IBM RS 6000 SP is one of the most successful commercially ...
Throughput and latency are critical parameters in multiprocessor interconnection networks. These par...
A message transport mechanism which provides highbandwidth low-latency interprocessor communication ...
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication in...
Abstract: In this paper, we present several enhanced network techniques which are appropriate for VL...
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is propose...
The IBM RS/6000 SP is one of the most successful commercially available multicomputers. SP owes its ...
Recent increases in the pin bandwidth of integrated-circuits has motivated an increase in the degree...
Modern network applications demand low-latency traffic engineering in the presence of network failur...
Abstract — The increasing wire delay constraints in deep sub-micron VLSI designs have led to the eme...
. As interconnection networks grow larger and larger, the need for reliable message delivery in the...
The design of a new adaptive virtual cut-through router for torus networks is presented in this pape...
This paper describes a router which is the key component of a scalable asynchronous on-chip and inte...