An Array Architecture for Reconfigurable Datapath

This thesis presents the design of a reconfigurable datapath suitable for use in constructing a reconfigurable microprocessor. The datapath design is based on a 2-D planar array of identical tiles that use an SRAM-based programming technology. Tiles in one dimension can be configured to define the width of the operands in the datapath. Tiles in the other dimension are used to define the logical operations performed on operands in the datapath. To illustrate the generality of the concept, the execution units of five different load/store pipelined RISC CPUs are mapped to the proposed tile array. A brief discussion on the implementation of the control section of reconfigurable microprocessors is also provided. The datapath architecture is modelled and simulated using VHDL. SPARC machine code of an integer ALU instruction sequence is used as a test vehicle in the simulations. Qiang Wang An Array Architecture for Reconfigurable Datapaths Master of Applied Science, 1993 Department of El..