Rectification Method for Lookup-Table Type FPGA's

Field programmable gate array (FPGA) makes rapid prototyping an easier task, and is useful in many applications due to its growing speed and capacity. In this paper, we present a rectification method for look-up table type FPGA's. Instead of changing the netlist of a circuit, we only modify functionality realized by look-up tables and keep the netlist equal so that there will be no change on the delay of the circuit. We formalize the problem using characteristic functions and present a redesign method based on Boolean relation techniques. 1 Introduction Field Programmable Gate Array (FPGA) is an important technology which has recently attracted much attention due to its advantage of rapid prototyping. There has also been increasing interest in using FPGA's for low-volume production of ASIC designs. Not a few papers have been published so far on logic synthesis for FPGA's, for example, Chortle and its successors Chortle-crf and Chortle-d by Francis et al. [10, 9, 11], DAG-map by Cong ..