In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be the width of the wire at position x, 0 x L. We show that the optimal wire-sizing function that minimizes the Elmore delay through the wire is f(x) = ae \Gammabx , where a ? 0 and b ? 0 are constants that can be computed in O(1) time. In the case where lower bound (L ? 0) and upper bound (U ? 0) on the wire widths are given, we show that the optimal wire-sizing function f(x) is a truncated version of ae \Gammabx that can also be determined in O(1) time. Our wire-sizing formula can be iteratively applied to optimally size the wire segments in a routing tree. 1 Introduction As VLSI technology continues to scale down, interconnect delay h...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cable...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Abstract- In this paper, two issues about wire width are investigated. The first one is that “Is the...
In this paper, by using calculus of variations, we determine the op-timal shape for a wire under the...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cable...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
Abstract — This paper considers simultaneous gate and wire sizing for general very large scale integ...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Abstract- In this paper, two issues about wire width are investigated. The first one is that “Is the...
In this paper, by using calculus of variations, we determine the op-timal shape for a wire under the...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An interconnect joining a source and a sink is divided into fixed-length uniform-width wire segments...
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergenc...
Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cable...