A Proposed SEU Tolerant Dynamic Random Access Memory (DRAM) Cell

A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a selfcompensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over conventional 1-T DRAM cells. I. INTRODUCTION The merger of commercial and space/military integrated circuit technologies is an increasingly important goal. Important factors leading toward this merger are the high speed, integration density, processing power, and reduced power consumption of the state-of-the-art commercial technologies. The expense of traditional radiation-hardened and military-qualified integrated circuits (IC's) is also..