. In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on reseeding of single polynomial LFSR's as well as LFSR's with fully programmable polynomials. Full programmability gives much better encoding efficiency. For a testcube with s carebits we need only s+4 bits in contrast to s+19 bits for reseeding of single polynomials, but since it involves solving systems of nonlinear equations it is not applicable to realistic cases. We propose a new BIST scheme where the generator can operate according to a number of primitive polynomials. The testcubes are encoded as the polynomial identifier and a seed. We present models of the encoding efficiency of this scheme and demonstrate, both theoretica...
Many stream ciphers employ linear feedback shift registers (LFSRs) to generate pseudorandom sequence...
Current methodologies for built-in test pattern generation usually employ a predetermined linear fee...
Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testin...
In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on ...
A comparative analysis of the encoding efficiency of built-in-self-test (BIST) schemes based on rese...
In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear ...
A viable technique [7] in built-in self-test (BIST)[2] is to generate test patterns pseudo-exhaustiv...
We consider a class of weak feedback polynomials for LFSRs in the nonlinear combiner. When feedback ...
We present a generalization of a class of characteristic polynomials used for linear feedback shift ...
We present a generalization of a class of characteristic polynomials used for linear feedback shift ...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
Abstract — This paper deals with the vital role of primitive polynomials for designing PN sequence g...
An approach for input data compaction in the testing of circuits using scan and partial scan has rec...
Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to com...
A class of codes similar to that presented by Bossen and Yau [2] and Stone [5] is constructed. Becau...
Many stream ciphers employ linear feedback shift registers (LFSRs) to generate pseudorandom sequence...
Current methodologies for built-in test pattern generation usually employ a predetermined linear fee...
Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testin...
In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on ...
A comparative analysis of the encoding efficiency of built-in-self-test (BIST) schemes based on rese...
In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear ...
A viable technique [7] in built-in self-test (BIST)[2] is to generate test patterns pseudo-exhaustiv...
We consider a class of weak feedback polynomials for LFSRs in the nonlinear combiner. When feedback ...
We present a generalization of a class of characteristic polynomials used for linear feedback shift ...
We present a generalization of a class of characteristic polynomials used for linear feedback shift ...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test da...
Abstract — This paper deals with the vital role of primitive polynomials for designing PN sequence g...
An approach for input data compaction in the testing of circuits using scan and partial scan has rec...
Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to com...
A class of codes similar to that presented by Bossen and Yau [2] and Stone [5] is constructed. Becau...
Many stream ciphers employ linear feedback shift registers (LFSRs) to generate pseudorandom sequence...
Current methodologies for built-in test pattern generation usually employ a predetermined linear fee...
Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern Generators for testin...