An Accurate Power and Timing Modeling Technique Applied To A Low-Power ROM Compiler

Large memories require too much computing resources to be fully extracted and simulated. In this paper we present an accurate power and timing modeling technique that significantly reduces characterization resources. The model is based on current controlled generators, and can be used in several regular structures. Lowpower memories are more easily characterized using this technique, since they are block partitioned. Moreover, this modeling technique is fully parameterable. It is very useful for developing and optimizing memory compilers efficiently. It has been successfully applied to characterize and improve performances of a low-power ROM compiler. 1 Introduction Since entering the era of 'system on a chip', large embedded memories with high throughputs and efficient power management architectures have become more and more necessary [1]. Such modules can be generated by dedicated compilers that enable the system designer to choose the appropriate memory features, for example, the g..