The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together the di®erent partitioning results within one level using superpositions we crossover to a mixture of experts one. This approach is improved applying genetic algorithms. We present two new partitioning algorithms (experts), the Backward-Cone-Concentration algorithm (n-BCC) and the Minimum-Overlap Cone-Cluster algorithm (MOCC), both of them taking cones as fundamental units for building partitions. 1 Introduction Logic design for ...
Genetic Algorithms (GAs) are robust techniques based on natural selection that can be used to solve ...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem form...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accel...
The application of Evolutionary Algorithms in hierarchical model partitioning for parallel system si...
Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its of...
This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-par...
Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interc...
An important stage in circuit design is placement, where components are assigned to physical locatio...
This work goals are SIMULA classes to model experts sessions so that each expert has his own start i...
We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which i...
The implementation and evaluation of several algorithms for the solution of the partitioning pro...
Abstract. The problem of partitioning appears in several areas ranging from VLSI, parallel programmi...
Genetic Algorithms (GAs) are robust techniques based on natural selection that can be used to solve ...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem form...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
The partitioning of complex processor models on the gate and register-transfer level for parallel fu...
Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accel...
The application of Evolutionary Algorithms in hierarchical model partitioning for parallel system si...
Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its of...
This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-par...
Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interc...
An important stage in circuit design is placement, where components are assigned to physical locatio...
This work goals are SIMULA classes to model experts sessions so that each expert has his own start i...
We present a novel genetic algorithm-based partitioning scheme for multichip modules (MCM's) which i...
The implementation and evaluation of several algorithms for the solution of the partitioning pro...
Abstract. The problem of partitioning appears in several areas ranging from VLSI, parallel programmi...
Genetic Algorithms (GAs) are robust techniques based on natural selection that can be used to solve ...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem form...