Experiments On Simulating Pram On Complete Network And On Mesh Of Buses

Parallel Random Access Machine, PRAM, is the most popular abstract model of the parallel computation. In PRAM model there is a collection of processors that have a shared memory, contrary to the distributed memory model where each processor only has local memory and processors are connected each other via a network. PRAM hides details of the machine architecture from programmer. In this paper, we experimentally investigate the simulation of PRAM on two distributed architectures of low latency: on the complete network and the on mesh of buses. Simulations are based on randomized hashing of shared memory and two strategies of delayed routing. Experiments show that with suitable simulation parameters, a PRAM step can be simulated in 5-10 clock cycles. This work is supported by Academy of Finland project 2 1. INTRODUCTION A criterion for classification of parallel architectures is how they use memory. In shared memory model (SMM) processors have a shared memory and no or little local m..