Scalable VLSI Design for Fast GF(p) Montgomery Inverse Computation

This paper accelerates a scalable GF(p) Montgomery inversion hardware. The hardware is made of two parts a memory and a computing unit. We modified the original memory unit to include parallel shifting of all bits which was a task handled by the computing unit. The new hardware modeling, simulating, and synthesizing is performed through VHDL for several 160-bits designs showing interesting speedup to the inverse computation