A New Biasing Technique for the MOS transistor

This paper describes a new biasing technique for the MOS transistor. The MOS is biased by a Gate-to-Bulk voltage VGB. The value of VGB can be chosen according to the level of inversion required, strong or weak. The input signal, current or voltage can be fed from either the drain or the source terminal. The technique can be sued in the implementation of logarithmic and antilogarithmic functions with microampere current range. This in turn will enhance the speed of the device in this mode of operation compared to the traditional weak inversion biasing. The new approach was verified by simulation using HSPICE level 47 in 0.8um CMOS proces