This paper presents a low overhead, high performance cache coherence protocol designed to exploit high bandwidth point-to-point and broadcast features of optics. SPEED integrates the virtues of snoopy-based schemes and directory-based schemes into one efficient protocol. Directory-assist is used exclusively for read traffic to eliminate unnecessary broadcasts while snoopy-assist is used exclusively for write and synchronization traffic to reduce directory overhead and synchronization complexities. The proposed protocol has the potential to increase performance as a result of its global independence between read and write operations, concurrency in channel access, reduced contention, and efficient broadcast of coherence and synchronization ...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
Recent advances in the development of optical technologies suggest the possible emergence of broadca...
Abstract—Ever since industry has turned to parallelism instead of frequency scaling to improve proce...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
Click on the DOI link to access the article (may not be free).While addressing cache coherency in sh...
This paper studies the interaction between the access protocol used to provide arbitration for a wav...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
The effects of various cache coherence strategies are analyzed for a multiported shared memory multi...
The quest to improve performance forces designers to explore finer-grained multiprocessor machines. ...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...
Recent advances in the development of optical technologies suggest the possible emergence of broadca...
Abstract—Ever since industry has turned to parallelism instead of frequency scaling to improve proce...
As the number of cores increases on chip multiprocessors, coherence is fast becoming a central issue...
Click on the DOI link to access the article (may not be free).While addressing cache coherency in sh...
This paper studies the interaction between the access protocol used to provide arbitration for a wav...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
This paper considers a large scale, cache-based multiprocessor that is interconnected by a hierarchi...
The effects of various cache coherence strategies are analyzed for a multiported shared memory multi...
The quest to improve performance forces designers to explore finer-grained multiprocessor machines. ...
[[abstract]]A cache coherence protocol for a multiprocessor system. Each processor in the system has...
Due to VLSI lithography problems and the limitation of additional architectural enhancements uniproc...
Caches have the potential to provide multiprocessors with an automatic mechanism for reducing both n...
Parallel applications exhibit a wide variety of memory reference patterns. Designing a memory archit...
Directory-based cache coherence protocol is accepted as the common technique in large scale shared m...
This thesis presents a new cache coherence protocol for shared bus multicache systems, and addresses...