A Combining Switch for the NYU Ultracomputer

This report describes the combining switch that we have implemented for use in the 16 \Theta 16 processor/memory interconnection network of the NYU Ultracomputer prototype. Packaging, message types and message formats are described. Details are given about the internal logic of the two component types used in the network, including the systolic combining queue, the wait buffer and the ALU. Systolic combining queue designs with greater combining capability are sketched. 1 Combining switch architecture A combining switch has been fabricated for use in the\Omega network of the NYU Ultracomputer prototype [3]. A 2 \Theta 2 switch node is composed of four each of two types of custom VLSI chips: forward path and return path components (Figure 1). Control for the switch is distributed as tri-state selection logic in each chip. The routing information is included in the message. Flow control avoids the necessity of acknowledgement for messages and allows pre-computation of signals that cont..