Cost Analysis of a New Algorithmic-Based Soft-Error Tolerant Architecture

A new ABFT architecture is proposed to tolerate multiple soft-errors with low overheads. It memorizes operands on a stack upon error detection and corrects errors by recomputing. This allows uninterrupted input data streams to be processed without data loss. 1: Introduction Several methods based on physical, electrical or logical principles have been proposed to reduce the susceptibility to error in digital systems. A system-level method, called Algorithmic-Based Fault Tolerance (ABFT), was originally proposed to obtain fault-tolerant processor array systems [1]. ABFT is a concurrent error detection/correction technique with relatively low hardware and time redundancy. This method operates on encoded input data sets and produces encoded output data. This on-line fault-tolerance scheme was successfully applied to many applications, such as Fourier Transform [2, 3, 4, 5, 6] and solving matrix equations [7, 8, 9, 10]. Some theoretical ABFT hardware and time overhead bounds have been publ..