Simulation of Multicache Parallel Graph Reduction

  • Andrew Bennett
  • Paul H J Kelly
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Publication date
January 1992

Abstract

Parallel graph reduction is a simple model for parallel program execution which uses the shared-memory abstraction for all communication and synchronisation between processors. Shared memory is used under a strict access regime with single assignment and blocking reads. In this paper we present the design of an efficient and accurate multiprocessor simulation scheme suitable to work with a parallel graph reducer and use the simulator to study the performance and pattern of access of a suite of benchmark programs. Threads are never migrated to another processor by the parallel graph reducer, and the effect of this scheduling policy is investigated. 1 Motivation and Overview Successful implementations of parallel graph reduction have been bu...

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