This paper presents a sensitivity-based wiresizing algorithm for interconnect delay optimization of lossy transmission line topology under MCM technologies. Our approach computes the maximum delay and its sensitivities with respect to the widths of wires in the topology via high order moments based on an exact moment matching model[6]. Compared with other approaches, it achieves analytical sensitivity computation and calculates higher order moments (sensitivities) recursively from lower order moments for tree network. It can yield optimal wiresizing solution for interconnect delay minimization. Experiments show that the delay estimation using high order moments is very accurate compared with SPICE simulation and our approach can reduce the ...
The inaccuracy of Elmore delay [3] for interconnect delay estimation is well-documented. However it ...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
The design of system level interconnects to meet signal integrity objectives is a challenging proble...
In this paper, we study the interconnect layout optimization problem under a higher order resistance...
Optimization of transient responses of highspeed VLSI interconnects modeled by distributed coupled t...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model ...
The main challenge for developing accurate and efficient delay metrics has been the prediction of d...
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model ...
In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. ...
An efficient approach is presented for time-domain sensitivity analysis of lossy multiconductor tran...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. ...
The inaccuracy of Elmore delay [3] for interconnect delay estimation is well-documented. However it ...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
The design of system level interconnects to meet signal integrity objectives is a challenging proble...
In this paper, we study the interconnect layout optimization problem under a higher order resistance...
Optimization of transient responses of highspeed VLSI interconnects modeled by distributed coupled t...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model ...
The main challenge for developing accurate and efficient delay metrics has been the prediction of d...
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model ...
In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. ...
An efficient approach is presented for time-domain sensitivity analysis of lossy multiconductor tran...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
In this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC t...
In this paper, we develop a set of delay estimation models with consideration of various interconnec...
Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. ...
The inaccuracy of Elmore delay [3] for interconnect delay estimation is well-documented. However it ...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
The design of system level interconnects to meet signal integrity objectives is a challenging proble...