: By the end of the decade, as VLSI integration levels continue to increase, building a multiprocessor system on a single chip will become feasible. In this paper, we propose to analyze the tradeoffs involved in designing such a chip, and specifically address whether to allocate available chip area to larger caches or to large numbers of processors. Using the dimensions of the Alpha 21064 microprocessor as a basis, we determine several candidate configurations which vary in cache size and number of processors, and evaluate them in terms of both processing power and cycle time. We then investigate fine tuning the architecture in order to further improve performance, by trading off the number of processors for a larger TLB size. Our results s...
As integrated circuit density increases, computer architects face the interesting problem of how bes...
Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficie...
Power constraints led to the end of exponential growth in single–processor performance, which charac...
Increasing levels of VLSI integration present new opportunities, and new challenges, for designers o...
As the performance gap between processors and main memory continues to widen, increasingly aggressiv...
In this paper, we propose several different data and instruction cache configurations and analyze th...
Continued advances in circuit integration technology has ushered in the era of chip multiprocessor (...
Single-ISA heterogeneous multicore processors have gained substantial interest over the past few yea...
Demands for flexible processing has moved general-purpose processing into the data path of networks....
Designers of chip multiprocessors will increasingly be called upon to optimize for a combination of ...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
: We present a methodology for comprehensively evaluating architectural and technological alternativ...
A balanced increase of memory bandwidth and computational capabilities is going to be one of the tre...
Hardware design for high performance computing appears to be reaching its limits on several fronts. ...
The continued decrease in transistor size and the increasing delay of wires relative to transistor s...
As integrated circuit density increases, computer architects face the interesting problem of how bes...
Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficie...
Power constraints led to the end of exponential growth in single–processor performance, which charac...
Increasing levels of VLSI integration present new opportunities, and new challenges, for designers o...
As the performance gap between processors and main memory continues to widen, increasingly aggressiv...
In this paper, we propose several different data and instruction cache configurations and analyze th...
Continued advances in circuit integration technology has ushered in the era of chip multiprocessor (...
Single-ISA heterogeneous multicore processors have gained substantial interest over the past few yea...
Demands for flexible processing has moved general-purpose processing into the data path of networks....
Designers of chip multiprocessors will increasingly be called upon to optimize for a combination of ...
With each technology generation we get more transistors per chip. Whilst processor frequencies have ...
: We present a methodology for comprehensively evaluating architectural and technological alternativ...
A balanced increase of memory bandwidth and computational capabilities is going to be one of the tre...
Hardware design for high performance computing appears to be reaching its limits on several fronts. ...
The continued decrease in transistor size and the increasing delay of wires relative to transistor s...
As integrated circuit density increases, computer architects face the interesting problem of how bes...
Caches consume a significant amount of energy in modern microprocessors. To design an energy-efficie...
Power constraints led to the end of exponential growth in single–processor performance, which charac...