A high-speed VLSI chip for parallel image decorrelation

We present here the architecture and design of a special purpose CMOS VLSI chip for high-speed parallel image decorrelation/inverse decorrelation scheme which is to be used for efficient real-time losslesss image compression/ decompression. The chip is designed for one processing element of the parallel architecture that performs the image decorrelation/inverse decorrelation. The architecture is based on an efficient parallel scheme, namely perfect shuffle image decorrelation scheme. A prototype 1-¯m CMOS VLSI chip has been designed, verified and fabricated. The design of the chip is highly pipelined and can achieve a throughput of about 120 Mbits/s with a clock rate of 15 MHz(Single phase) for both decorrelation and inverse decorrelation. Hence if four of these chips operate simultaneously we can have a decorrelation/inverse decorrelation rate of approximately 500 Mbits/s which can match the image compression rates required by many high-speed applications. Keywords: VLSI, JPEG, Image ..