Memory (EEPROM) with 2 kbits (256 × 8-bit) non-volatile storage. By using an internal redundant storage code, it is fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. Data bytes are received and transmitted via the serial I 2 C-bus. Up to eight PCF85102C-2 devices may be connected to the I 2 C-bus. Chip select is accomplished by three address inputs (A0, A1 and A2). 2. Features ■ Low power CMOS: ◆ 2.0 mA maximum operating current ◆ maximum standby current 10 µA (at 6.0 V), typical 4 µA ■ Non-volatile storage of 2 kbits organized as 256...
A new low-power EEPROM circuit for sensor interface circuit is introduced in this paper. The calibra...
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower tha...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Memory (EEPROM) with 4 kbits (512 × 8-bit) non-volatile storage. By using an internal redundant stor...
In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) usin...
In the last decades, the computing technology experienced tremendous developments. For instance, tra...
This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique ...
Most server-grade memory systems provide Chipkill-Correct error protection at the expense of power a...
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling ...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
[[abstract]]A novel EEPROM memory cell with new program and erase operations fabricated by standard ...
● 123 powerful instructions – most single clock cycle execution ● 32 x 8 general purpose working reg...
Various applications require the storage of program code or calibration data inside a non-volatile m...
Non volatile memories hold 30% of the global volume of semiconductor memory market nowadays. The gen...
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower tha...
A new low-power EEPROM circuit for sensor interface circuit is introduced in this paper. The calibra...
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower tha...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...
Memory (EEPROM) with 4 kbits (512 × 8-bit) non-volatile storage. By using an internal redundant stor...
In this paper, a novel single-poly electrically erasable programmable read-only memory (EEPROM) usin...
In the last decades, the computing technology experienced tremendous developments. For instance, tra...
This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique ...
Most server-grade memory systems provide Chipkill-Correct error protection at the expense of power a...
A new single-poly-EEPROM cell compatible with standard CMOS processes is proposed. A pMOS tunneling ...
One of the most effective techniques to reduce a processor\u27s power consumption is to reduce suppl...
[[abstract]]A novel EEPROM memory cell with new program and erase operations fabricated by standard ...
● 123 powerful instructions – most single clock cycle execution ● 32 x 8 general purpose working reg...
Various applications require the storage of program code or calibration data inside a non-volatile m...
Non volatile memories hold 30% of the global volume of semiconductor memory market nowadays. The gen...
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower tha...
A new low-power EEPROM circuit for sensor interface circuit is introduced in this paper. The calibra...
This work analyzes the stochastic behavior of writing to embedded flash memory at voltages lower tha...
textFuture computing platforms will increasingly demand more stringent memory resiliency mechanisms ...