Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems

Abstract—We reduce cache supply voltage below the normally acceptable VDDMIN, in order to improve overall many– core system energy efficiency. Based on the observation that cache lines contain mostly one hard faulty cell at these ultralow supply voltages, we exploit existing double-error correcting triple-error detecting codes, together with cache line disabling, to handle both soft and hard cache faults, thus enabling reliable ultra-low supply voltage cache operation. Compared to the nextbest approach in the research literature, the proposed method reduces system energy consumption by up to 25 % and energyexecution time product by nearly 10%, while introducing only 0.28 % storage overhead and marginal instruction per cycle degradation, when the target yield loss rate is 1/1000. Index Terms—Cache, fault tolerance, low-power design, manycore, very-large-scale integration (VLSI). I