Optimization of Interconnect Geometry for High-Performance Microprocessors

The goals of the work presented in this paper were to estimate quantitatively the impact of interconnect technology parameters on the performance of high-end microprocessors and to use this information to optimize the interconnect geometry within the constraints imposed by the process. The 64-bit PA 8000 microprocessor was used as a test case. by Khalid Rahmat and Soo-Young Oh For the past two decades the driving force for integrated circuits has been scaling of both the devices and the interconnect. This has yielded faster and denser chips with ever increasing functionality. Today’s high-performance microprocessors have 4 to 5 million logic transistors 1,2,3 and operate in the frequency range of 200 to 250 MHz. To stay on the trend for CPU performance gains, the next-generation processors will likely have clock speeds of 400 to 500 MHz and have up to 10 million transistors for the logic implementation. 4 The design and manufacture of systems that provide such performance will require careful attention to all process, device, and circuit issues. In particular, the interconnect system for the next-generation CPUs needs to sustain the burden of connecting 10 million transistors with 5 to 6 metal layers over a 2-cm die with a clock cycle of 2 to 2.5 ns. Because the interconnect system affect