Variation-Aware Variable Latency Design

Although typical digital circuits are designed so that the clock period satisfies worst-case path delay constraints, the average input excitation often completes computation in less than a clock cycle. Variable latency units (VLUs) allow for improved throughput by allowing one clock cycle for some computations, and two clock cycles for others, using hold logic to differentiate between the two cases. However, they may experience significant throughput losses due to the effects of process variations. We develop a combined presilicon-postsilicon technique for variation-aware VLU design that ensures high throughputs across all manufactured chips. We achieve this by identifying path clusters at the presilicon stage, such that each element of a path cluster is likely to be similarly critical in a manufactured part. We use sensors to determine which path clusters is critical at the postsilicon stage and then activate the appropriate hold logics. Practically, for a small number of path clusters, significant improvements in throughput are achievable. On a set of 32nm PTM-based ISCAS89 circuits, our scheme offers 15.1 % throughput enhancements with only 3.3 % area overhead. The idea can be illustrated through the example of a 6-bit ripple carry adder (RCA) shown in Fig. 1 [5]. With unit gate delays, the conventional single-cycle fixed-latency circuit has a cycle time, Tclk = 13 units, equal to the delay of its longest path, corresponding to a throughput, η1 = 1/13. The VLU implementation of this adder operates at a reduced cycle time, Tclk < 13. For Tclk = 9, assuming that all primary input signals are mutually independent and have signal probabilities of 50%, 18.75 % of the input patterns violate Tclk, and the VLU allows these to complete execution in two cycles. Under the 50 % assumption above, since each pattern is equiprobable, the average VLU delay is 0.8125 × 9 + 0.1875 × 18 = 10.69 units, and the throughput η2 = 1/10.69 is 21.6 % better