Abstract — Large amount of software for embedded digital signal processing systems is written in assembly language. Software pipelining of loops is necessary to exploit the full potential of Very Long Instruction Word (VLIW) processors. For both understanding software pipelined loops and reverse compiling them to high level language code the software pipelined loops must be de-pipelined back to the original loops. In this paper we present technique for software de-pipelining of nested loops, demonstrate it with an example and evaluate the benefits of some software pipelined nested loops. Keywords—software pipelining; de-pipelining; nested loops; DSP.
The paper investigates the interaction between software pipelining and different software prefetchin...
ii The high performance of today’s microprocessors is achieved mainly by fast, multipleissuing hardw...
This paper presents an approach to software pipelining of nested loops. While several papers have ad...
Software pipelining is a loop optimization technique used to speed up loop execution. It is widely i...
In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs hav...
Software pipelining is one of the most important optimization techniques to increase the parallelism...
International audienceSoftware pipelining (or modulo scheduling) is a powerful back-end optimization...
Software pipelining is an effective technique to reduce cycle count by exploiting instruction level ...
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and supers...
Software Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the...
International audienceThis paper is a step towards enabling multidimensional software pipelining of ...
This paper tackles the problem of providing correct information about program variable values in a s...
International audienceThis paper tackles the problem of providing correct information about program ...
In this paper, we propose a compiler method for software pipelining of loop nests on multi-core chip...
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or f...
The paper investigates the interaction between software pipelining and different software prefetchin...
ii The high performance of today’s microprocessors is achieved mainly by fast, multipleissuing hardw...
This paper presents an approach to software pipelining of nested loops. While several papers have ad...
Software pipelining is a loop optimization technique used to speed up loop execution. It is widely i...
In order to fully utilize the instruction level parallelism of VLIW DSP processors, DSP programs hav...
Software pipelining is one of the most important optimization techniques to increase the parallelism...
International audienceSoftware pipelining (or modulo scheduling) is a powerful back-end optimization...
Software pipelining is an effective technique to reduce cycle count by exploiting instruction level ...
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and supers...
Software Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the...
International audienceThis paper is a step towards enabling multidimensional software pipelining of ...
This paper tackles the problem of providing correct information about program variable values in a s...
International audienceThis paper tackles the problem of providing correct information about program ...
In this paper, we propose a compiler method for software pipelining of loop nests on multi-core chip...
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or f...
The paper investigates the interaction between software pipelining and different software prefetchin...
ii The high performance of today’s microprocessors is achieved mainly by fast, multipleissuing hardw...
This paper presents an approach to software pipelining of nested loops. While several papers have ad...